Motivated by the desire for both lower cost and higher performance, integrated circuit (IC) technology has moved throughout its history toward building larger and larger circuits comprising more and more devices. The development of random access memory (RAM) integrated circuits have shared in this movement. In the sense of containing a larger number of memory cells where each cell can store one bit, the larger a RAM becomes, the more difficult and expensive it is to test it. Also, the more expensive the cost of a defect in the circuit, as a single defect can result in the loss of the whole chip.
Not only are RAM's fabricated as stand-alone chips, but they are also built embedded as function blocks in other integrated circuits. Such integrated circuits could be designed and produced as standard chips intended for a variety of applications and as application specific integrated circuits (ASIC's).
With the size and complexity of modern integrated circuits including RAM's, testing has become an important issue. Size and cost constraints limit the area on the integrated circuit available for use as wire bonding pads, flip-chip solder bumps, and the like with the resultant effect of limiting access to the various functioning areas of the chip. So, not all functions of the chip are externally available for direct test. Even if connections to some of these areas were available, the long traces and additional external circuitry necessary to access them would introduce signal delays that could render the results of such testing questionable. Thus of necessity, some testing circuitry is now often included on-chip.
On-chip testing also has its share of difficulties as chip area available for testing is limited, as is accessibility to nodes for testing. Delays introduced by trace lengths also continue to be an issue. In addition unless the chip is designed for mass production, the costs associated with design, manufacturing, and test can be prohibitive.
Additional, redundant circuitry is often included in large integrated circuits. Techniques available, as for example laser fusing, permit the removal of defective parts of the IC and its replacement with the redundant part. This process is cost effective, since on average the added cost of the redundant circuitry is less than the cost associated with the yield loss without the additional circuitry. The addition of redundant circuitry is especially valuable for circuits with repeating structure function blocks, such as RAM and other types of memory. In such circuits a limited number of defective cells can be replaced with the redundant cells embedded in the circuitry. Once again, however, unless the chip is designed for mass production, design costs can be prohibitive.
Thus since current on-chip techniques for testing RAM function blocks typically require a substantial area on the chip and are typically somewhat removed from the tested area introducing propagation delay errors, there is a need for enhanced means for testing RAM circuits on-chip.